The following invention relates to an analog to digital convertor and, in particular, to a high speed analog to digital convertor which provides conversion from the analog domain to the digital domain with a high degree of precision and resolution.
Analog to digital converters are used to convert data such as audio from an analog format to a digital format. One way in which ADC circuits have functioned in the past is by sampling an analog wave form and converting a voltage representing the analog signal into a pulse width modulated signal. The pulse widths are then directly proportional to the input analog voltage. The width of the pulse can be converted into a digital number and a series of these variable width pulses then follows the input analog voltage. This conversion method has been generally sufficient to accurately digitize commercial quality analog audio and video signals.
There are several problems, however, with this method of analog to digital conversion. Clocked PWM convertors, such as delta-sigma convertors having, for example, a timer resolution of n, add large amounts of high frequency noise power to the digitized incoming analog signal. This high frequency noise must be filtered out, typically by using a multiple tap digital FIR filter at the cost of additional long-latency, extensive circuitry.
A typical pulse width modulated signal generator is shown in FIG. 1. A control voltage at the xe2x80x9chighxe2x80x9d input to an operational amplifier produces a pulse width modulated signal at the output that is proportional to the magnitude of the control voltage. Another typical type of pulse width modulation circuit is shown in FIG. 2A. FIG. 2A is what is known as a delta-sigma modulator. The problem with such modulators lies in the feedback loop which introduces noise at the analog front end of the modulator. The noise comes from clock pulses that control the sampling of the analog signal. The feedback loop drives the input waveform to a zero crossing where it is sampled by a clock pulse. There is however a degree of uncertainty in the position of the zero crossing relative to the timing of the clock pulse. It is this error that shows up as high frequency noise.
The present invention provides an analog to digital convertor utilizing a pulse width modulator (PWM) circuit responsive to an analog parameter of an analog signal in which the PWM circuit generates a PWM pulse having a period proportional to the analog parameter. A counter generates a plurality of counter pulses during the period of the PWM pulse where the number of the counter pulses is proportional to the PWM pulse width. At the same time, a subcycle pulse generator generates a series of subcycle pulses during the PWM pulse period. The subcycle pulse are much shorter than the counter pulses. A latch circuit latches the highest state of the subcycle pulse generator at a predetermined time relative to the termination of the PWM pulse. A logic circuit counts both the number of counter pulses generated during the PWM pulse and the highest logic state of the subcycle pulse generator and latches both numbers. The latched number of counter pulses forms the most significant bits of a digital number and the latched logic state of the subcycle pulse generator forms the least significant bits of a digital number which represents the value of the analog input parameter.
The subcycle pulse generator may comprise a ring oscillator having a plurality of taps where each tap represents a fractional timing interval or delay which is a subdivision of the period of each of the counter pulses. A high speed follower circuit which is triggered by outputs of the ring oscillator generates data pulses which accurately follow the output state of the ring oscillator. In this way, a state which represents an amount of delay from the leading edge of each of the counter pulses is converted into digital data which can be latched, then digitized to represent the least significant bits of the digital number.
The advantage of this circuit is that it provides much higher resolution for the digital output number without the attendant high frequency noise caused by most PWM type analog to digital convertors.